HYB25D256800CT Datasheet, PDF (78/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

5.2
Read Command: Data Output Timing
Figure 40 shows DQS versus DQ Timing during read burst.
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Timing Diagrams
DQS
DQ
t_{DQSQ max}
t_QH
t_QH (Data output hold time from DQS)
t_DQSQ and t_QH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.
t._DQSQ and t_QH both apply to each of the four relevant edges of DQS.
t_{DQSQ max.} is used to determine the worst case setup time for controller data capture.
t_QH is used to determine the worst case hold time for controller data capture.
Figure 40 Data Output (Read), Timing Burst Length = 4
Data Sheet
78
Rev. 1.6, 2004-12