HYB25D256800CT Datasheet, PDF (15/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Pin Configuration
Table 4 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
F3, 47
UDM I
SSTL Data Mask Upper Byte
F7, 20
LDM
I
SSTL Data Mask Lower Byte
Power Supplies
F1, 49
A9, B2, C8,
D2, E8, 3, 9,
15, 55, 61
V_REF
V_DDQ
AI
—
PWR —
I/O Reference Voltage
I/O Driver Power Supply
A7, F8, M3, V_DD
M7, 1, 18, 33
PWR —
Power Supply
A1, B8, C2, V_SSQ
D8, E2, 6, 12,
52, 58, 64
PWR —
Power Supply
F2, 34
V_SS
Not Connected
PWR —
Power Supply
A2, 65
NC
NC
—
Not Connected
Note: ×4 organization
A8, 2
NC
NC
—
Not Connected
Note: ×4 organization
B1, 63
NC
NC
—
Not Connected
Note: ×8 and ×4 organisation
B9, 4
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C1, 60
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C3, 59
NC
NC
—
Not Connected
Note: ×4 organization
C7, 8
NC
NC
—
Not Connected
Note: ×4 organization
C9, 7
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D1, 57
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D9, 10
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E1, 54
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E7, 16
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E9, 13
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
F7, 20
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
Data Sheet
15
Rev. 1.6, 2004-12