HYB25D256800CT Datasheet, PDF (10/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Overview
1.2
Description
The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read or write access for the
256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.Read and write accesses to the DDR SDRAM
are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a
Read or Write command. The address bits registered coincident with the Active command are used to select the
bank and row to be accessed. The address bits registered coincident with the Read or Write command are used
to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 2 Ordering Information for Lead Containing Products
Product Type²⁾
Org. CAS-RCD-RP Clock CAS-RCD-RP Clock
Latencies
(MHz) Latencies (MHz)
HYB25D256800CT–5 ×8 3-3-3
200 2.5-3-3
166
HYB25D256160CT–5 ×16
HYB25D256800CT–6 ×8 2.5-3-3
166 2-3-3
133
HYB25D256800CT(L)–6 ×8
HYB25D256160CT–6 ×16
HYB25D256400CT–7 ×4
143
HYB25D256400CC–5 ×4 3-3-3
200 2.5-3-3
166
HYB25D256800CC–5 ×8
HYB25D256160CC–5 ×16
HYB25D256400CC–6 ×4 2.5-3-3
166 2-3-3
133
HYB25D256800CC–6 ×8
HYB25D256160CC–6 ×16
Speed
DDR400B
DDR333
DDR266A
DDR400B
DDR333
Package
P-TSOPII-66
P-TFBGA-60
Data Sheet
10
Rev. 1.6, 2004-12