HYB25D256800CT Datasheet, PDF (40/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
NOP
BA a, COL n
CL=2
PRE
BA a or all
NOP
NOP
t_RP
DOa-n
ACT
BA a, ROW
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BA a, COL n
NOP
PRE
BA a or all
CL=2.5
NOP
NOP
t_RP
DOa-n
ACT
BA a, ROW
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Don’t Care
Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
40
Rev. 1.6, 2004-12