HYB25D256800CT Datasheet, PDF (37/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

CK
CK
Command
Address
DQS
DQ
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
CAS Latency = 2
Read
BAa, COL n
Read
BAa, COL x
CL=2
Read
BAa, COL b
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n’ DOa-x DOa-x’ DOa-b DOa-b’ DOa-g
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BAa, COL n
Read
Read
BAa, COL x
BAa, COL b
CL=2.5
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n’ DOa-x DOa-x’ DOa-b DOa-b’
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Don’t Care
Data Sheet
37
Rev. 1.6, 2004-12