HYB25D256800CT Datasheet, PDF (77/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Timing Diagrams
5
Timing Diagrams
The timing diagrams in this chapter give an overview of possible and recommended command sequences.
5.1
Write Command: Data Input Timing
Figure 39 shows DQS versus DQ and DM Timing during write burst.
DQS
DQ
DM
t_DQSL
t_DQSH
t_DH
t_DS
DI n
t_DH
t_DS
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Figure 39 Data Input (Write), Timing Burst Length = 4
Data Sheet
77
Rev. 1.6, 2004-12