HYB25D256800CT Datasheet, PDF (35/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

CK
CK
Command
Address
DQS
DQ
CK
CK
Command
Address
DQS
DQ
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
Read
BAa, COL b
NOP
DOa-n
NOP
NOP
DOa-b
CAS Latency = 2.5
Read
BAa, COL n
NOP
Read
BAa,COL b
CL=2.5
NOP
DOa- n
NOP
NOP
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 11 Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
Don’t Care
Data Sheet
35
Rev. 1.6, 2004-12