HYB25D256800CT Datasheet, PDF (79/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

5.3
Initialization and Mode Register Set Command
Figure 41 shows the timing diagram for initialization and Mode Register Sets.
Figure 41 Initialize and Mode Register Sets
Data Sheet
79
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Timing Diagrams
Rev. 1.6, 2004-12