TC1797_14 Datasheet, PDF (28/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Introduction
• The Boot ROM interface.
• The Emulation Memory interface.
• The Local Memory Bus LMB slave interface.
Following memories are controlled by and belong to the PMU0:
• 2 Mbyte of Program Flash memory (PFlash)
• 64 Kbyte of Data Flash memory (DFlash, represents 16 Kbyte EEPROM)
• 16 Kbyte of Boot ROM (BROM)
• 8 Kbyte Overlay RAM (OVRAM)
In the TC1797 an additional PMU is included with only a subset of PMU0’s submodules:
• The Flash command and fetch control interface but only for Program Flash.
• The Local Memory Bus LMB slave interface.
The following memories are controlled and belong to the PMU1:
• 2 Mbyte of Program Flash memory (PFlash).
Because of its independence from PMU0 this second PMU enables additional
functionality: Read while Write (RWW), Write while Write (WWW) or concurrent data and
instruction accesses, if those are operating on different PMUs.
Data Sheet
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V1.3, 2014-08