TC1797_14 Datasheet, PDF (158/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

5.3.4 Power, Pad and Reset Timing
TC1797
Electrical Parameters
Table 18 Power, Pad and Reset Timing Parameters
Parameter
Symbol
Min.
Values
Unit Note /
Typ. Max.
Test Con
dition
Min. V_DDP voltage to ensure
defined pad states¹⁾
V_DDPPA CC 0.6
Oscillator start-up time²⁾
t_OSCS CC –
Minimum PORST active time t_POA
after power supplies are stable
at operating levels
SR 10
––
V–
– 10 ms –
––
ms –
ESR0 pulse width
t_HD CC Program –
–
mable³⁾⁵⁾
f_SYS –
PORST rise time
t_POR SR –
Setup time to PORST rising t_POS SR 0
edge⁴⁾
– 50 ms –
––
ns –
Hold time from PORST rising t_POH SR 100
edge
––
ns ^TESTMODE
TRST
Setup time to ESR0 rising
edge
t_HDS SR 0
––
ns –
Hold time from ESR0 rising
edge
Ports inactive after PORST
reset active⁶⁾⁷⁾
t_HDH SR 16 ×
–
1/f_SYS5)
t_PIP CC –
–
–
ns ^HWCFG
150 ns –
Ports inactive after ESR0 reset t_PI
active (and for all logic)
Power on Reset Boot Time⁸⁾ t_BP
CC –
CC –
– 8 × 1/ ns –
f_SYS
– 2.5 ms –
Application Reset Boot Time t_B
at f_CPU=180MHz⁹⁾¹⁰⁾
CC 125
– 575 μs –
1) This parameter is valid under assumption that PORST signal is constantly at low level during the power-
up/power-down of the V_DDP.
2) t_OSCS is defined from the moment when V_DDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of
0,3 × V_DDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (f_FPI) cycles.
Data Sheet
154
V1.3, 2014-08