TC1797_14 Datasheet, PDF (141/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
Class F Pads, CMOS Mode (V_DDP = 3.13 to 3.47 V = 3.3V ± 5%)
Input low voltage V_ILF
-0.3 – 0.36 × V –
Class F pins
SR
V_DDP
Input high voltage V_IHF
0.60 × –
Class F pins
SR V_DDP
V_DDP+ V
0.3 or
max.
Whatever is lower
3.6
Input hysteresis
Class F pins
Input leakage
current Class F
pins
HYSF 0.05 × –
CC V_DDP
I_OZF
–
–
–
V
±3000 nA ((V_DDP/2)-1) < V_IN
<
±6000
((V_DDP/2)+1)
Otherwise²⁾
Output low voltage V_OLF
–
6)
CC
– 0.4
V I_OL = 2 mA
Output high
voltage^{2) 6)}
V_OHF
2.4
––
CC _{VDDP - –}
–
0.4
V I_OH = -2 mA
V I_OH = -1.4 mA
Class D Pads
See ADC Characteristics –
––
––
1) Not subject to production test, verified by design / characterization.
2) Only one of these parameters is tested, the other is verified by design characterization
3) Maximum resistance of the driver R_DSON, defined for P_MOS / N_MOS transistor separately:
25 / 20 Ω for strong driver mode, I_{OH / L} < 2 mA,
200 / 150 Ω for medium driver mode, I_{OH / L} < 400 uA,
600 / 400 Ω for weak driver mode, I_{OH / L} < 100 uA,
verified by design / characterization.
4) Function verified by design, value verified by design characterization.
Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce.
It cannot be guaranteed that it suppresses switching due to external system noise.
5) V_DDEBU = 2.5 V ± 5%. For V_DDEBU = 3.3 ± 5% see class A2 pads.
6) The following constraint applies to an LVDS pair used in CMOS mode: only one pin of a pair should be used
as output, the other should be used as input, or both pins should be used as inputs. Using both pins as outputs
is not recommended because of the higher crosstalk between them.
Data Sheet
137
V1.3, 2014-08