TC1797_14 Datasheet, PDF (20/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Introduction
2.2.3 CPU Cores of the TC1797
The TC1797 includes a high Performance CPU and a Peripheral Control Processor.
2.2.3.1 High-performance 32-bit CPU
This chapter gives an overview about the TriCore 1 architecture.
TriCore (TC1.3.1) Architectural Highlights
• Unified RISC MCU/DSP
• 32-bit architecture with 4 Gbytes unified data, program, and input/output address
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• Fast automatic context-switching
• Multiply-accumulate unit
• Floating point unit
• Saturating integer arithmetic
• High-performance on-chip peripheral bus (FPI Bus)
• Register based design with multiple variable register banks
• Bit handling
• Packed data operations
• Zero overhead loop
• Precise exceptions
• Flexible power management
High-efficiency TriCore Instruction Set
• 16/32-bit instructions for reduced code size
• Data types include: Boolean, array of bits, character, signed and unsigned integer,
integer with saturation, signed fraction, double-word integers, and IEEE-754 single-
precision floating point
• Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit double-
word data formats
• Powerful instruction set
• Flexible and efficient addressing mode for high code density
Integrated CPU related On-Chip Memories
• Instruction memory: 40 KB total. After reset, configured into:¹⁾
– 40 Kbyte Scratch-Pad RAM (SPRAM)
– 0 Kbyte Instruction Cache (ICACHE)
• Data memory: 128 KB total. After reset, configured into:¹⁾
– 128 Kbyte Local Data RAM (LDRAM)
1) Software configurable. Available options are described in the CPU chapter.
Data Sheet
16
V1.3, 2014-08