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TC1797_14 Datasheet, PDF (183/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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5.3.11.3 SSC Master/Slave Mode Timing
TC1797
Electrical Parameters
Table 31
Parameter
SSC Master/Slave Mode Timing
(Operating Conditions apply), CL = 50 pF
Symbol
Values
Min.
Typ. Max.
Master Mode Timing
SCLK clock period
t50 CC 2 Ã TSSC â
â
MTSR/SLSOx delay from t51 CC 0
SCLK rising edge
â8
MRST setup to SCLK
falling edge
t52 SR 13
ââ
MRST hold from SCLK
falling edge
t53 SR 0
ââ
Slave Mode Timing
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK
latching edge
t54 SR 4 Ã TSSC â
â
t55/t54 SR 45
â 55
t56 SR TSSC + 5 â
â
MTSR hold from SCLK
latching edge
t57 SR TSSC + 5 â
â
SLSI setup to first SCLK t58 SR TSSC + 5 â
â
shift edge
SLSI hold from last SCLK t59 SR 7
latching edge
ââ
MRST delay from SCLK
shift edge
t60 CC 0
â 15
SLSI to valid data on MRST t61 CC â
â 12
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 Ã TSSC.
3) TSSCmin = TSYS = 1/fSYS. When fSYS = 90 MHz, t50 = 22.2 ns.
4) Fractional divider switched off, SSC internal baud rate generation used.
Unit Note /
Test Con
dition
ns 1)2)3)
ns â
ns 3)
ns 3)
ns 1)3)
%â
ns 3)4)
ns 3)4)
ns 3)
ns â
ns â
ns â
Data Sheet
179
V1.3, 2014-08
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