TC1797_14 Datasheet, PDF (167/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
5.3.9 DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 23
DAP Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
DAP0 clock period
t₁₁ SR 12.5 –
–
ns –
DAP0 high time
t₁₂ SR 4
–
–
ns –
DAP0 low time
t₁₃ SR 4
–
–
ns –
DAP0 clock rise time
t₁₄ SR –
–
2
ns –
DAP0 clock fall time
t₁₅ SR –
–
2
ns –
DAP1 setup
to DAP0 rising edge
t₁₆ SR 6
–
–
ns –
DAP1 hold
t₁₇ SR 6
–
–
ns –
after DAP0 rising edge
DAP1 valid
t₁₉ SR 8
–
–
ns 80 MHz,
per DAP0 clock period¹⁾
C_L = 20 pF
t₁₉ SR 10
–
–
ns 40 MHz,
C_L = 50 pF
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t₁₁
0.5 VDDP
t_{1 5}
t_{1 2}
t_{1 3}
Figure 32 Test Clock Timing (DAP0)
0.9 V_DDP
t₁₄
0.1 V_DDP
MC_DAP0
Data Sheet
163
V1.3, 2014-08