TC1797_14 Datasheet, PDF (161/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency f_LMB results in a higher absolute maximum jitter value.
Figure 28 gives the jitter curves for several K2 / f_LMB combinations.
±10.0
D_{m ns}
±8.0
±7.0
±6.0
f_LMB = 50 MHz (K2 = 8)
f_LMB = 100 MHz (K2 = 4)
±4.0
f_LMB = 180 MHz (K2 = 4)
f_LMB = 150 MHz (K2 = 4)
±2.0
±1.0
f_LMB = 100 MHz (K2 = 8)
f_LMB = 50 MHz (K2 = 16)
±0.0
0
20
40
60
80
D_m = Max. jitter
m = Number of consecutive f_LMB periods
K2 = K2-divider of PLL
100
120
oo
m
TC1797_PLL_JITT_M
Figure 28 Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies f_LMB
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed C_L = 20 pF with the maximum driver and sharp edge, except the E-Ray
output pins, which can be loaded with C_L = 25 pF. In case of applications with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V_DDOSC3 at pin E26 and V_SSOSC at pin F25, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V_DDOSC at pin F26 and V_SSOSC at pin F25, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
Data Sheet
157
V1.3, 2014-08