TC1797_14 Datasheet, PDF (176/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
5.3.10.2 EBU Burst Mode Access Timing
V_SS = 0 V;V_DD = 1.5 V ± 5%; V_DDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
T_A = -40 °C to +125 °C; C_L = 35 pF;
Table 27 EBU Burst Mode Read / Write Access Timing Parameters¹⁾
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Con
dition
Output delay from BFCLKO t₁₀ CC -2
–
active edge²⁾
2
ns –
RD and RD/WR active/inactive t₁₂ CC -2
–
after BFCLKO active edge³⁾
2
ns –
CSx output delay from
BFCLKO active edge³⁾
t₂₁ CC -2.5 –
1.5 ns –
ADV active/inactive after
BFCLKO active edge⁴⁾
t₂₂ CC -2
–
2
ns –
BAA active/inactive after
BFCLKO active edge⁴⁾
t_22a CC -2.5 –
1.5 ns –
Data setup to BFCLKI rising t₂₃ SR 3
–
–
ns –
edge⁵⁾
Data hold from BFCLKI rising t₂₄ SR 0
–
–
ns –
edge⁵⁾
WAIT setup (low or high) to t₂₅ SR 3
–
–
ns –
BFCLKI rising edge⁵⁾
WAIT hold (low or high) from t₂₆ SR 0
–
–
ns –
BFCLKI rising edge⁵⁾
1) Not subject to production test, verified by design/characterization.
2) This is a default parameter which are applicable to all timings which are not explicitly covered by the other
parameters.
3) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock
divider ratio.
Negative minimum values for these parameters mean that the last data read during a burst may be corrupted.
However, with clock feedback enabled, this value is oversampling not required for the LMB transaction and
will be discarded.
4) This parameter is valid for BUSCONx.EBSE = 1 and BUSAPx.EXTCLK = 00_B.
For BUSCONx.EBSE = 1 and other values of BUSAPx.EXTCLK, ADV and BAA will be delayed by 1 / 2 of the
LMB bus clock period T_CPU = 1 / f_CPU.
For BUSCONx. EBSE = 0 and BUSAPx.EXTCLK = 11_B, add 2 LMB clock periods.
For BUSCONx. EBSE = 0 and other values of BUSAPx.EXTCLK add 1 LMB clock period.
Data Sheet
172
V1.3, 2014-08