TC1797_14 Datasheet, PDF (181/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
3) The min./max. TCLK low/high times t₁₁/t₁₂ include the PLL jitter of f_SYS. Fractional divider settings must be
regarded additionally to t₁₁ / t₁₂.
4) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5) The following formula is valid: t₂₁ + t₂₂ = t₂₀
6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters.
7) The RCLK max. input rise/fall times are best case parameters for f_SYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Data Sheet
177
V1.3, 2014-08