TC1797_14 Datasheet, PDF (177/192 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
5) If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as
at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply.
BFCLKI ₁₎
BFCLKO
A[23:0]
Address
Phase(s)
t₁₀
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Burst Start Address
t₂₂
t₂₂
ADV
Recovery Next Addr.
Phase(s) Phase(s)
t₁₀
Next
Addr.
t₂₂
t21
CS[3:0]
CSCOMB
t₁₂
RD
RD/WR
t22a
BAA
t21
t21
t₁₂
t22a
D[31:0]
(32-Bit)
t24
t₂₃
Data (Addr+0)
t24
t₂₃
Data (Addr+4)
D[15:0]
(16-Bit)
WAIT
t26
t25
Data (Addr+0) Data (Addr+2)
1) _{Output delays are always referenced to BCLKO. The reference clock for input}
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
Figure 39 EBU Burst Mode Read / Write Access Timing
Data Sheet
173
V1.3, 2014-08