TLE6266G Datasheet, PDF (21/50 Pages) Infineon Technologies AG – System Basis Chip

Target Datasheet TLE 6266
Mode State
Normal Mode
Normal Mode
Cyclic HS ON
CSN,
SPI word*
SPI
normal
mode
SPI
cyclic HS
ON
Watchdog trigger bit
=SPI bit0**
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
SPI
cyclic HS
ON
SPI
normal
mode
Normal Mode
Vbat Stdby
t
closed
window
Window watchdog***
open
window
closed
window
open
window
long open window
HS3
long open window
closed
window
open
window
closed
window
missing trigger =
timeout =
Watchdog Reset
open
window
Watchdog reset pulse time t_WDR
t
long open window
t
t
PWM
PWM trigger
PWM
trigger
Vs
Bus
Wake
t
Vcc CANL
trigger
CAN Bus message
CANH
t
Input filtering time t_IFT
* for the exact timing relations between CSN
and SPI-DI and -DO word please look at
datasheet fig. 11,12,13,14,15
** bit0 is transfered with the SPI input word
BUT
the watchdog trigger is set, after readout of
the SPI input bit = CSN LOW to HIGH
(see arrows at CSN signal)
*** for a correct watchdog triggering:
closed window must always exceed 12 cycles
open window is max. 20 cycles
long open window is max. 128 cycles
otherwise
a watchdog reset will be generated
Figure 8 Cyclic Wake with CAN Message Wake-up
7.2 Wake-Up via Wake Pin
CANL is pulled to Vs. A signal transition at the wake pin WK from LOW to HIGH (rising
edge) causes a wake up and automatic transition into the cyclic HS ON mode (see
Figure 9). HS3 is activated again and also the long open window of the watchdog
mechanism. The watchdog has to be triggered correctly from that time on. If the signal
at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again.
This wake up via the wake pin is comming from an external circuitry (switch, etc.) and
is not flagged by the RxD.
Version 1.06
22
2002-11-26