TLE6266G Datasheet, PDF (13/50 Pages) Infineon Technologies AG – System Basis Chip

Target Datasheet TLE 6266
6.4 Low Dropout Voltage Regulator
The TLE6266 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance
is less than ± 2%. In addition the regulator circuit drives the internal loads like the CAN-
transceiver circuit. In the cyclic wake HS OFF operation mode the voltage regulator is
switched on and off by a control mechanism (see Chapter 6.5).
The current limitation of the LDO is set to typ. 180mA, to grant that the external capacitor
can be charged quickly. In normal operating mode the external current should be less
then 45mA. This has to guaranteed by the system architecture.
An external reverse current protection is recommended to prevent the output capacitor
from being discharged by negative transients or low input voltage.
Stability of the output voltage is guaranteed for output capacitors C_VCC ³ 100 nF.
Nevertheless a lot of applications require a much larger output capacitance to buffer the
output voltage in case of low input voltage or negative transients. Furthermore the due
function of e.g. the reset and 3V-supervisor circuit are supported by a larger output
capacitance because of their reaction times. Therefore a output capacitance
C_VCC ³ 22 µF is recommended.
6.5 LDO activation during Cyclic Wake HS OFF
During the cyclic wake HS OFF mode, the LDO is switched on and off, depending on the
output voltage level, which is monitored internaly. Figure 6 shows a detailed flowchart
of the V_cc control loop and also a graph of the V_cc voltage and the thresholds in this
mode. The voltage regulator is switched on as soon as the voltage at V_CC falls below the
load-threshold to charge an external capacitor for 1ms. When the nominal voltage level
is reached again, the voltage regulator is automatically deactivated to minimize the
current consumption. The period of charging/decharging is dependant on the external
stabilization capacitor at V_CC.
6.6 3V-Supervisor
If the output voltage falls below the 3V-supervisor threshold V_ST, an internal flip-flop is
set LOW. The SPI output bit 7 monitors this. In normal operation this flip-flop has to be
activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data
of the microcontroller might be damaged or the application is connected to V_S the first
time.
The 3V supervisor uses a comparator to monitor the voltage. Additional, there is a
possibility to disable this comparator in order to reduce the current consumption. To do
this, set SPI input bit 15 first and in the next step set SPI input bit 7.
Version 1.06
14
2002-11-26