TLE6266G Datasheet, PDF (14/50 Pages) Infineon Technologies AG – System Basis Chip

Target Datasheet TLE 6266
Vcc
5
4
t_CHARGE
Charge Diagram
Yes
V_{CC TH}
V_{RESET TH}
t
No
Monitor V_cc in Cyclic wake
HS OFF Mode
Vcc
V_cc > load threshold
V_{CC TH} ?
Vcc
No
V_cc< reset threshold
V_{RESET TH}
for t > 3µs ?
Charge of V_cc for 1ms
(Switch on LDO)
Yes
RESET after filtering-
time
Figure 6 LDO activation flowchart for the cyclic wake HS OFF mode
6.7 SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see Table 6) is read in via the data
input DI, and this is synchronized with the clock input CLK supplied by the µC. The
diagnosis word appears synchroniously at the data output DO (see Table 7).
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point, thereby
releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The sate
of DO is shifted out of the output register after every rising edge on CLK. For more details
of the SPI timing please refer to Figure 11 to 15.
CAN Bus Wiring Failure direct Read-out
The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission
directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to
HIGH resets the SPI diagnosis bit 0.
SPI CLK Monitoring during Cyclic Wake Mode
The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic
wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
Version 1.06
15
2002-11-26