TLE6266G Datasheet, PDF (18/50 Pages) Infineon Technologies AG – System Basis Chip

Target Datasheet TLE 6266
Moreover the switch is disabled when a reset occurs. After the second correct triggered
watchdog, the switch is released for usage.
6.13 Low Side Switches 1 & 2
The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA.
Their on-resistance is 1.5 W typ. @ 25°C. This switches are controlled via the SPI input
bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates
the switches to protect them.
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 4
flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation
of the TLE 6266 by switching off functions of minor priority before the temperature
threshold of the thermal shutdown is reached. The SPI output bits 5/6 are giving a
feedback about current status (ON/OFF) of OUTL1/OUTL2. As soon as the under-
voltage condition of the supply voltage is met (V_S < V_UVOFF), the switches are
automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI
diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are disabled when a reset
occurs. After the second correct triggered watchdog, the switches are released for
usage.
6.14 Wake Up Pin
This pin is used to wake up the TLE 6266 with an external signal from the µC. The
feature is active during cyclic HS OFF mode to switch the transceiver into the cyclic HS
ON mode before starting up the µC. A correct wake up signal is a rising edge at the WK
pin during cyclic HS OFF mode. The WK pin has an implemented pull down resistance.
6.15 Timebase Test
This test is useful to measure the internal cycle time of the TLE 6266. The µC may use
this information to activate special functions or routines in the cyclic wake mode, which
are depending on timing.(e.g. to switch on/off a LED after a certain number of cyclic HS
ON conditions). During the long open window the timebase test is not available.
To measure the internal cyclic timing, the SPI input bit 3 and 4 have to be set HIGH. Then
the HS3 switch is automatically enabled for 3 times during the closed window of the
watchdog (see Figure 7). A correct SPI input word (with IBit 3 and 4 set HIGH) has to
be read in first, to activate the timebase test. Due to he fact, that the input command gets
activated after the CSN LOW to HIGH transition, it takes t=t_SYNC to activate the timebase
test. If this SPI input command is given within the open window, t_SYNC=max 500ns. If the
command is given during closed window (this is not a watchdog trigger command) the
synchronisation t_SYNC can last up to 500µs.
Version 1.06
19
2002-11-26