CA91L8260B Datasheet, PDF (92/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

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3. Processor Bus Interface
3.3.2
3.3.2.1
3.3.2.2
Data Phase
The data phase deals with the control of transaction length.
Transaction Length
The PB Slave supports a set of the data transfer sizes supported by the embedded PowerPC family. All
data transfer sizes supported by the PowerSpan II PB Slave are illustrated in Table 16. Burst transfers
are indicated by the assertion of Processor Bus Transfer Burst (PB_TBST_). The shaded regions
indicate transaction sizes unique to the PowerQUICC II.
Table 16: PowerSpan II PB Transfer Sizes
Transfer Size
Byte
Half-word
Tri-byte
Word
Five bytes
Six bytes
Seven bytes
Double Word (DW)
Extended Double (PowerQUICC II
only)
Extended Triple (PowerQUICC II only)
Burst (Quad DW)
Bytes
1
2
3
4
5
6
7
8
16
24
32
PB_TBST
1
1
1
1
1
1
1
1
1
PB_TSIZ[0]
0
0
0
0
0
0
0
0
1
1
1
0
0
PB_TSIZ[1:3]
001
010
011
100
101
110
111
000
001
010
010
Data Alignment
Embedded processor bus transfer sizes and alignments, defined in Table 16 and Table 17, are supported
by the PB Slave for transaction accesses. The shaded table cells in Table 17 show transactions that
support the PowerPC 7400 processor.
Table 17 lists the size and alignment transactions less than or equal to 8 bytes. PowerSpan II register
accesses are limited to 4 bytes or less.
The PowerSpan II port size is 64-bit.
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com