CA91L8260B Datasheet, PDF (49/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

2. PCI Interface
49
2.3.2.2
Address Translation
The address generated by the PCI Master is dependent on the use of address translation in the source
target image (see “PCI-1 Target Image x Control Register” on page 268) or slave image (see
“Processor Bus Slave Image x Control Register” on page 287). When address translation is enabled —
by setting the TA_EN bit in PCI Target or PB Slave Image Control Register — PowerSpan II produces
the PCI address using the following inputs:
• the incoming address from the source bus
• the block size of the slave or target image
• the translation offset
For address translation going from the processor bus to PCI, see “Processor Bus Interface” on page 83.
For an example of address translation control going from PCI to PCI, see “PCI-1 Target Image x
Translation Address Register” on page 274.
When address translation is disabled, the address generated by the PCI Master is the same as the
address on the source bus.
Integrated Device Technology
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PowerSpan II User Manual
80A1010_MA001_09