CA91L8260B Datasheet, PDF (51/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

2. PCI Interface
51
2.3.3.3
The PowerSpan II PCI Master generates a Memory Read command selection according to the rules in
Table 9.
Table 9: PowerSpan II PCI Master Read Commands
Internal Request of Transaction
Length
<= 8 bytes
<= CLINE[7:0] in Px_MISC0
> CLINE[7:0] in Px_MISC0
PCI Memory Read Command
Memory Read
Memory Read Line
Memory Read Multiple
The read amount presented to the PCI Master determines the command used. A Memory Read Line
command uses the burst length programmed into the CLINE[7:0] field in the “PCI-1 Miscellaneous 0
Register” on page 255. It is programmable to 16-, 32-, 64-, or 128 bytes.
If the PCI Master does not complete the burst read transaction before a target termination, it
completes the read with subsequent PCI read transactions at the appropriate address.
Parity Monitoring and Generation
PowerSpan II monitors Px_PAR#/Px_PAR64# when it accepts data as a PCI master during a read, and
drives Px_PAR#/Px_PAR64# when it provides data as a PCI master during a write. PowerSpan II also
drives Px_PAR#/Px_PAR64# during the address phase of a transaction when it is a PCI master. In both
address and data phases, the Px_PAR#/Px_PAR64# signal provides even parity for Px_C/BE#[3:0] and
Px_AD[31:0]. Even parity is enabled Px_C/BE#[7:4] and Px_AD[63:32] for PCI-1 in 64-bit mode.
PowerSpan II parity response is enabled through the Parity Error Response (PERESP) bit in the “PCI-1
Control and Status Register.” on page 251. Data parity errors are reported through the assertion of
Px_PERR# when the PERESP bit is set. The Detected Parity Error (D_PE) bit in the “PCI-1 Control
and Status Register.” on page 251 is set when PowerSpan II encounters a parity error as a PCI master
on any transaction. PowerSpan II records an error condition in the event of a parity error (see “Error
Handling” on page 157).
The Master Data Parity Detected (MDP_D) bit in the “PCI-1 Control and Status Register.” on page 251
is set if the PERESP bit is enabled and either PowerSpan II is the master of the transaction where it
asserts PERR#, or the addressed target asserts PERR#. If the transfer originated from the Processor
Interface, then PowerSpan II sets the MDP_D bit and the Px_PB_ERR_EN bit in the “Interrupt Enable
Register 1” on page 334. PowerSpan II then asserts an interrupt (see “Interrupt Handling” on
page 145).
PowerSpan II continues with the transaction independent of any parity errors reported during
the transaction.
Integrated Device Technology
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PowerSpan II User Manual
80A1010_MA001_09