CA91L8260B Datasheet, PDF (111/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

3. Processor Bus Interface
111
3.4.3
3.4.3.1
Terminations
The PB master uses the following pins as termination signals for individual data beats and data tenure:
• Address Retry (PB_ARTRY_): This signal terminates the entire data tenure and schedules the
transaction to be rerun. No data is transferred.
• Transfer Acknowledge (PB_TA_): This signal is asserted by the external slave to indicate the
successful transfer of a single beat transaction, or each 8 byte quantity transferred for a burst.
• Data Valid (PB_DVAL_): This signal is asserted by the external slave to indicate the successful
transfer of a quantity of data. The PowerQUICC II provides this pin to support the termination of
extended cycles. The external slave asserts this pin once for each successful 8 byte transfer.
PB_TA_ is asserted, with PB_DVAL_, on the final transfer of the transaction. The slave uses
PB_TA_ and/or PB_DVAL_ to insert wait states. The PB master ignores PB_DVAL_ when the
EXTCYC bit cleared in the “Processor Bus Miscellaneous Control and Status Register” on
page 304.
• Transfer Error Acknowledge (PB_TEA): This signal indicates an unrecoverable error and causes
the PB master to immediately terminate the data tenure.
Errors
The PB master detects three error conditions:
• data parity on reads
• assertion of PB_TEA_ by external slave
• expiration of maximum retry counter (MAX_RETRY bit in the “Processor Bus Miscellaneous
Control and Status Register” on page 304).
See “Error Handling” on page 157 and “Interrupt Handling” on page 145 for a full description of error
logging support and associated interrupt mapping options.
Integrated Device Technology
www.idt.com
PowerSpan II User Manual
80A1010_MA001_09