CA91L8260B Datasheet, PDF (162/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

162
8.3
8. Error Handling
• Assertion of PB_TEA_, expiration of max retry counter:
— All writes
– Stop the transaction
– Purge the entire source transaction from the Switching Fabric
– Error status sent to DMA channel registers (for DMA writes)
— All reads
– Stop the transaction
– Latch error condition for propagation back to source
PCI Interface Errors
In the following discussion Px refers to the PCI Interface that detected the error and Py refers to the
alternate PCI Interface.
The Px master and target detect error conditions while participating in PCI bus transactions. In addition
to the “Interrupt Status Register 1” on page 329 (ISR1), the Px Interface provides the following
reporting mechanisms:
• External signaling of the following signals:
— Target-Abort
— Master-Abort
— Address parity errors
— Data parity errors
• Detection of Target-Abort.
• Standard PCI error reporting in “PCI-1 Control and Status Register.” on page 251 (Px_CSR).
• Capture of specific parameters from the transaction that caused the error:
— “PCI-1 Bus Error Control and Status Register” on page 281 (Px_ERRCS), which logs PCI
command
— “PCI-1 Address Error Log Register” on page 282 (Px_AERR), which logs PCI Address
(Px_AD)
Table 41 on page 163 itemizes the error cases detected and reported by the Px master and the Px target.
Error logging in Px_ERRCS and Px_AERR is triggered for each of these error cases
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
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