CA91L8260B Datasheet, PDF (297/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

12. Register Descriptions
297
For a Configuration Type 0 cycle — with the TYPE bit set to 0 — an access of the PCI Configuration
Data register performs a corresponding Configuration Type 0 cycle on either PCI bus. Programming
the Device Number causes the assertion of one of the upper address lines, AD[31:11], during the
address phase of the Configuration Type 0 cycle. This is shown in Table 77.
Table 77: PCI AD[31:11] lines asserted during Configuration Type 0 cycles
DEV_NUM[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101-11111
AD[31:11]
0000 0000 0000 0001 0000 0
0000 0000 0000 0010 0000 0
0000 0000 0000 0100 0000 0
0000 0000 0000 1000 0000 0
0000 0000 0001 0000 0000 0
0000 0000 0010 0000 0000 0
0000 0000 0100 0000 0000 0
0000 0000 1000 0000 0000 0
0000 0001 0000 0000 0000 0
0000 0010 0000 0000 0000 0
0000 0100 0000 0000 0000 0
0000 1000 0000 0000 0000 0
0001 0000 0000 0000 0000 0
0010 0000 0000 0000 0000 0
0100 0000 0000 0000 0000 0
1000 0000 0000 0000 0000 0
0000 0000 0000 0000 0000 1
0000 0000 0000 0000 0001 0
0000 0000 0000 0000 0010 0
0000 0000 0000 0000 0100 0
0000 0000 0000 0000 1000 0
0000 0000 0000 0000 0000 0
The remaining address lines are:
• AD[10:8] = FUNC_NUM[2:0]
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PowerSpan II User Manual
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