CA91L8260B Datasheet, PDF (322/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

322
12. Register Descriptions
12.5.43
I²C/EEPROM Interface Control and Status Register
This register supports the PowerSpan II I²C/EEPROM interface.
An I²C bus cycle is initiated by writing to this register. Software must wait for the ACT bit to be zero
before starting a new I²C cycle. When the ACT bit is 1, writes to this register have no effect and the
DATA field is undefined.
Both the ACT bit and the ERR bit are updated five PB clocks after a PB write
completion (PB_TA asserted)
The PCI VPD EEPROM Chip Select (VPD_CS) bit, in the “Miscellaneous Control and Status
Register” on page 318, selects the EEPROM where VPD resides. If VPD_CS is 000b, then VPD starts
at address offset 0x40 of the first EEPROM. For all other values of VPD_CS, VPD starts at address
offset 0x00 of the specified EEPROM.
Register Name: I2C_CSR
Register Offset: 0x408
PCI
Bits
31-24
23-16
15-08
07-00
ACT
DEV_CODE
ERR
Function
ADDR
DATA
CS
PowerSpan II Reserved
PB
Bits
0-7
8-15
RW
16-23
24-31
Name
ADDR[7:0]
DATA[7:0]
DEV_CODE[3:0]
CS[2:0]
RW
Type
R/W
R/W
R/W
R/W
R/W
Reset
By
G_RST
G_RST
G_RST
G_RST
G_RST
Reset
State
0
0
1010
0
0
Function
Specifies I²C device address to be accessed.
Specifies the required data for a write. Holds the data at
the end of a read.
Device select. I²C 4-bit device code.
Chip Select
0=read
1=write
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com