CA91L8260B Datasheet, PDF (177/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

177
10.
Endian Mapping
Big-endian refers to a method of formatting data where address 0 (or the smallest address referencing
to the data) points to the most significant byte of the data.
Little-endian refers to a method of formatting data where address 0 (or the smallest address referencing
the data) points to the least significant byte of the data.
Data in a system must be consistent; that is, the system must be entirely big-endian or little-endian.
This chapter describes the endian mapping system used in PowerSpan II. The following topics are
discussed:
• “Conventions” on page 177
• “Processor Bus and PowerSpan II Register Transfers” on page 179
• “Processor Bus and PCI Transfers” on page 183
10.1
10.2
Overview
PowerSpan II supports a flexible endian conversion scheme for the following transactions involving
the Processor Bus (PB) Interface:
• Access of PowerSpan II registers from the PB Interface
• Transfers between the processor bus and PCI — both externally initiated and PowerSpan II DMA
initiated
No endian conversion is performed for transactions mapped between the two PCI interfaces:
PCI-1 and PCI-2.
Conventions
Table 46 illustrates the data bus lanes used to carry each byte of a multi-byte structure on PCI. PCI
stores multi-byte structures with little-endian byte ordering.
Table 46: PCI Byte Lane Definitions
Byte Address
PCI Byte Lanes
AD[2:0]
64-bit Transaction
32-bit Transaction
Lane Number Pins
AD[2]
Lane Number Pins
000
0
P1_AD[7:0]
0
0
Px_AD[7:0]
Integrated Device Technology
www.idt.com
PowerSpan II User Manual
80A1010_MA001_09