CA91L8260B Datasheet, PDF (76/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

76
2.6.8
2. PCI Interface
I₂O Standard Registers
This section defines the standard I₂O register set supported by PowerSpan II. These registers are
accessible within the PowerSpan II I₂O target image. In Table 10, all standards-based registers are in
italics.
Table 10: PowerSpan II I20 Target Image Map
Offset
(HEX)
Register
Mnemonic
Register Name
0x000-028
PowerSpan II Reserved
0x030
0x034
0x038
OPL_IS
I₂0 Outbound Post List Interrupt Status Register
OPL_IM
I₂0 Outbound Post List Interrupt Mask Register
PowerSpan II Reserved
0x040
0x044
0x048-[HOST_OIO]-4
IN_Q
I₂0 Inbound Queue
OUT_Q
I₂0 Outbound Queue
PowerSpan II Reserved
[HOST_OIO]
[HOST_OIO]+4-0xFF
HOST_OI
I₂O Host Outbound Index Register
PowerSpan II Reserved
0x100-xxx
I₂0 Inbound Message Frames
The I₂O Shell Interface is located in the first 4 Kbytes of the PowerSpan II I₂O target image. The I₂O
Inbound Message Frames occupies offsets above the 4 Kbyte point of the PowerSpan II I₂O target
image. The upper limit of the I₂O Inbound Message Frames is determined by the size of the PowerSpan
II I₂O target image, as defined by the PCI_I2O_CTL[BS] register.
The offset of the I₂O Host Outbound Index Register is programmed in the I₂O Host Outbound Index
Offset Register (HOST_OIO) of the PowerSpan II Register Map.
The following tables show the I₂O register definitions.
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com