CA91L8260B Datasheet, PDF (120/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

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4. DMA
4.3.1.1
4.3.1.2
Direct Mode Transfer Acknowledgment
The following registers are updated during a transfer and can be used to monitor status during DMA
channel activity:
• DMA Source Address (DMAx_SRC_ADDR) in the “DMA x Source Address Register” on
page 309
• DMA Destination Address (DMAx_DST_ADDR) in the “DMA x Destination Address Register”
on page 310
• Byte Count (BC[23:0]) field in the “DMA x Destination Address Register” on page 310.
Terminating a Direct Mode Transfer
The current Direct mode transfer can be stopped by writing 1 to the STOP_REQ bit in the “DMA x
General Control and Status Register” on page 314. When this occurs, the channel stops attempting to
buffer data from the source bus. When the remaining buffered source data is written to the destination
bus, the STOP status bit is set.
The channel can be restarted by clearing the STOP status bit (along with any other status bits) and then
writing a 1 to the GO bit.
Due to the pipelined nature of DMA channel requests, up to 256-bytes can be transferred after
the user programmed the initial stop request.
4.4
Linked-List Mode DMA Operation
In Linked-List (scatter-gather) mode, PowerSpan II steps through a linked series of command packets
in external memory. The DMA is configured with the starting address of this list and independently
reads command packets and executes the transfers specified.
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com