CA91L8260B Datasheet, PDF (266/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

266
12. Register Descriptions
12.5.12
PCI-1 Vital Product Data Capability Register
PowerSpan II only supports VPD access from the Primary PCI Interface. The Secondary PCI Interface
reads zero for VPD accesses. VPD writes have no effect.
VPD can also be disabled when the NXT_PTR bit in the “PCI-1 Compact PCI Hot Swap Control and
Status Register” on page 264 register is 0.
Register Name: P1_VPDC
Register Offset: 0E8
PCI
Bits
31-24
F
23-16
15-08
07-00
Function
Reserved
VPDA
NXT_PTR
CAP_ID
PB
Bits
0-7
8-15
16-23
24-31
Name
F
VPDA [7:0]
NXT_PTR [7:0]
CAP_ID [7:0]
Type
R/W
R/W
R
R
Reset
By
P1_RST
P1_RST
P1_RST
P1_RST
Reset
State
0
0x00
0x00
0x03
Function
Data Transfer Complete Flag
Indicates when the transfer between the VPD Data register
and the EEPROM is complete. Software clears the bit to
initiate a read and PowerSpan II sets the bit when the read
data is available in the VPD Data register. Software sets the
bit to initiate a write and PowerSpan II clears the bit to
indicate when the data has been transferred.
Vital Product Data Address
The 8-bit address specifies the VPD address offset for the
VPD-Read or VPD-Write to the serial EEPROM. When I2C
chip select 0 is used for the VPD EEPROM the VPD address
translates a maximum of 64 bytes and 192 bytes are
available for VPD. The first 64 bytes of VPD is VPD-Read
Only, and the remaining 128 bytes — 192 bytes if separate
256 byte EEPROM used for VPD — is VPD-Read/Write.
Next Pointer
VPD is the last Extended Capabilities Pointer
Capability ID
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com