CA91L8260B Datasheet, PDF (179/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

10. Endian Mapping
179
10.3
Processor Bus and PowerSpan II Register Transfers
The PowerSpan II PB Slave supports register accesses from a PowerPC operating in big-endian or
PowerPC little-endian mode. The endian conversion mode for processor access to PowerSpan II
registers is selected by programming the END bit in the “Processor Bus Register Image Base Address
Register” on page 295. The default mode is big-endian, which matches the default mode of the
processor bus.
PowerSpan II registers are little-endian structures. The endian conversion process provided by
PowerSpan II for processor bus accesses to its registers is designed to preserve the significance of the
programmer’s multi-byte structures or scalars. Endian conversion for access to PowerSpan II registers
from the processor is data invariant.
When the processor bus is operating in big-endian mode, the END bit must be set to big-endian mode.
In this case, the PowerSpan II PB slave maps the processor bus byte lanes to PowerSpan II register
addresses according to Table 48.
Integrated Device Technology
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PowerSpan II User Manual
80A1010_MA001_09