CA91L8260B Datasheet, PDF (313/439 Pages) Integrated Device Technology – PowerSpan II™ User Manual

12. Register Descriptions
313
12.5.38
DMA x Command Packet Pointer Register
This register specifies the 32-byte aligned address of the next command packet in the Linked-List for
channel DMAx. It is programmed by PowerSpan II from the Linked-list when loading the command
packet.
The DMAx_CPP register is updated at the start of a Linked-list transfer and remains constant
throughout the transfer. Writing to this register while the DMA is active has no effect.
For a Direct mode DMA transfer, this register does not need to be programmed.
Register Name: DMAx_CPP
Register Offset: 0x31C, 0x34C, 0x37C, 0x3AC
PCI
Bits
31-24
23-16
15-08
07-00
NCP
Function
NCP
NCP
NCP
PowerSpan II Reserved
LAST
PB
Bits
0-7
8-15
16-23
24-31
Name
NCP[31:5]
LAST
Type
R/W
R/W
Reset
By
G_RST
G_RST
Reset
State
0
0
Function
Next Command Packet Address.
Points to a 32-byte aligned memory location of a linked-list on
the port specified by the CP_PORT bit in the DMAx_ATTR
register.
Last Item
0 = more items in linked list
1 = last item in linked list
Integrated Device Technology
www.idt.com
PowerSpan II User Manual
80A1010_MA001_09