92HD92 Datasheet, PDF (69/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Address
EQRAM
Bits
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
Channel RIGHT Coefficients (24bit)
[47:24]
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F2_A1
EQ_COEF_F2_A2
EQ_COEF_F3_B0
EQ_COEF_F3_B1
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
EQ_COEF_F4_B2
EQ_COEF_F4_A1
EQ_COEF_F4_A2
EQ_PRESCALE
Channel LEFT Coefficients (24bit)
[23:00]
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F2_A1
EQ_COEF_F2_A2
EQ_COEF_F3_B0
EQ_COEF_F3_B1
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
EQ_COEF_F4_B2
EQ_COEF_F4_A1
EQ_COEF_F4_A2
EQ_PRESCALE
The EQRAM is programmed indirectly through the Control Bus in the following manner:
1) Write the 48-bit write data to the EQRAM_WRITE register
2) Write the target address to the EQ_ADDRESS register
3) Set bit 7 of the EQRAM_CTRL register
The write will occur when the EQRAM is not being accessed by the DSP audio processing routines. When complete
the hardware will automatically clear this bit.
Reading back from the EQRAM is done in the following manner:
1) Write target address to EQ_ADDR register
2) Set bit 6 of the EQRAM_CTRL register
When the hardware completes the read it will automatically clear this bit.
3) When bit 6 of the EQRAM_CTRL register has been cleared, read the 48bit data from the EQRAM_READ register.
2.29.2.35. EQRAM Read Data (0x30–0x35), EQRAM Write Data (0x36–3B) Registers
These two 48-bit registers (addressed as 12 8-bit registers) are 48-bit data holding registers used
when doing indirect writes/reads to the EQRAM.
These registers reset by POR/DAFG/ULR
]The EQRAM_WRITE will also reset by writing to NID22h verb 77F ]
Register Address
30h
EQRAM_READ[47:40]
verb FA0/7A0
Bit
Label
7:0 EQRD[47:40]
Type Default
Description
RW 0x00
48-bit data register, contains the contents of the most recent
EQRAM address read from the RAM. The address read will
have been specified by the EQRAM Address fields.
IDT™ CONFIDENTIAL
69
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 1.1 1/12
92HD92