92HD92 Datasheet, PDF (55/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset
Register Address
Bit
Label
7:6 RSVD
5
SAEN
4
AUXSWAP
0x08
verb F78/778
3
MCLKMS
2:0 MCLK[2:0]
Type Default
Description
RO 00
Reserved
RW 0
1 = Input enabled for I2S Secondary Audio
0 = Input disabled for Secondary Audio
RW 0
Swap Left and Right Samples of Aux Audio Output.
0 = Left sample first in frame
1 = Right sample first in frame
RW 1
MCLK master
0 = MCLK is an input
1 = MCLK is an output (not recommended in Aux Audio Mode
since 24/12MHz rates cant be supported and 112MHz internal
clock is imprecise but is useful for testing.)
RW 001
MCLK rate
000 = 24MHz (HDA BitClk)
001 = 12MHz (HDA BitClk/2)
010 = 22.5792MHz
011 = 11.2896MHZ
100 = 5.6448MHZ
101 = 28.224MHz
110 = 14.112MHz
111 = 7.056MHz
Note: The audio interface control is intended to be the same as implemented in non Aux Audio mode but is controlled
through the I2C interface rather than the HD Audio Bus.
2.29.2.5. PWRM Register
Power management in Aux Audio Mode
IDT™ CONFIDENTIAL
55
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92HD92