92HD92 Datasheet, PDF (54/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset.
Register Address
Bit
Label
7
TRI
0x07
verb F77/777
6:3 SCLK[3:0]
2:0 SR[2:0]
Type Default
Description
RW 0
TRI=1 & MS = 0 (Slave mode)
I2S_DOUT is hi-z (I2S_SCLK and I2S_LRCLK are inputs)
TRI=1 & MS = 1(Master mode)
I2S_DOUT, I2S_SCLK, and I2S_LRCLK are hi-z
RW 0000
SCLK rate
See table below
RW 100
Sample Rate
000 = 44.1KHz
001 = 88.2KHz
010= Reserved
011 = Reserved
100 = 48KHz
101 = 96KHz
110 = 192KHz
111 = Reserved
Note: The audio interface control is intended to be the same as implemented in non Aux Audio mode but is controlled
through the I2C interface rather than the HD Audio Bus.
SCLK[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Frequency
(MHz)
Auto
12.288
6.144
3.072
11.2896
5.6448
2.8224
Auto
16.128
8.064
4.032
7.056
3.528
1.764
PLL clock
divisor
Auto
147/16
147/32
147/64
10
20
40
Auto
7
14
28
16
32
64
suggested clocks/fr
sample rate ame
Notes
All
64 SCLK is always 64Fs (48KHz based rates have jitter)
192KHz
64
High jitter (<5nS)
96KHz
64
High jitter (<5nS)
48KHz
64
High jitter (<5nS)
88.2KHz
128
88.2KHz
64
44.1KHz
64
reserved
All
64/84
SCLK adjusts for sample rate. 44.1KHz based rates
are 64Fs and 48KHz based rates are 84Fs
192KHz
84
96KHz
84
48KHz
84
88.2KHz
80
44.1KHz
80
44.1KHz
40
reserved
2.29.2.4. AIC3 Register
Audio Interface (I2S) control in Aux Audio Mode.
IDT™ CONFIDENTIAL
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92HD92