92HD92 Datasheet, PDF (49/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Figure 20. Multiple Read Cycle
S
DA[6:0]
nW ACK
RA[7:0]
ACK Sr
DA[6:0]
R ACK
RD[7:0]
ACK
RD[7:0]
ACK
Set Register Address
Read Register @ RA[7:0]
Read Register
@ RA[7:0] + 1
RD[7:0]
nACK P
Read Register
@ RA[7:0] + n
2.29.2. I2C Registers
The CODEC that supports I2S I/O also supports a 2-wire (I2C and SMBUS compatible) interface for
control while in Aux Audio Mode. The interface supports up to 400KHz operation. All registers
(except for the reset register) are available when in normal mode through the HD Audio interface.
Most are implemented using vendor defined verbs but some (volume controls specifically) are sup-
ported through standard verbs at the pin widgets.
Register Name
R0(00h)
R1(01h)
R2(02h)
R3(03h)
R4(04h)
R5(05h)
RSVD
SPKVOLL
SPKVOL
R
RSVD
RSVD
RSVD
R6(06h) AIC1
R7(07h) AIC2
R8(08h) AIC3
R9(09h) PWRM
R10(0Ah)
R11(0Bh)
R12(0Ch)
R13(0Dh)
R14(0Eh)
R15(0Fh) RESET
R16(10h) STATUS
R17(11h) INIT
R18(12h) CONFIG1
Remarks
Reserved
SPKR Left volume
SPKR Right volume
Reserved
Reserved
Reserved
Audio Interface 1
Audio Interface 2
Audio Interface 3
Pwr Mgmt
Reset
BTL status
CONFIG1
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Defa
ult
SPKVOL_L[7:0]
30h
SPKVOL_R[7:0]
30h
SCLKIN
V
MS
LRSWA
P
LRP
WL[1:0]
FORMAT[1:0] 4Ah
TRI
SCLK[3:0]
SR[2:0]
04h
MCLKM
S
MCLK[2:0]
09h
HPPWD
SPKRP
WD
DMICP
WD
MCLKo
ut
AUXEn
03h
writing to this register resets all registers to their default state
limit1lat limit0lat
ch
ch
BPF
BYP
PRE
BYP
EQBYP
anabee
p_dc
byp
limit1
anabee
p_dc
coeff1
limit0
anabee
p_dc
coeff0
zerodet
_flag
initialize
HPF
BYP
00h
not
reset
00h
04h
60h
Table 20. I2C Registers
IDT™ CONFIDENTIAL
49
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD92