92HD92 Datasheet, PDF (57/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
2.29.2.8. INIT Register
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset
Register Address
0x11
CONFIG1
verb F81/781
Bit
Label
Type Default
Description
7:4 Reserved
RO 0
RESERVED
3
anabeep_dcbyp RW 0
1 = bypass analog Beep DC filter
2:1
anabeep_dc_coef
f
RW
0x2
0: dc_coef = 24’h004000;
1: dc_coef = 24’h001000;
2: dc_coef = 24’h000400;
3: dc_coef = 24’h000100;
0
Initialize
RW 0
1= Initialize/soft reset data path. Must be set when changing
the config0 or config1 registers.
2.29.2.9. CONFIG Register
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset
Register Address
0x12
CONFIG
verb F82/782
Bit
Label
7
BPFBYP
6
PREBYP
5
EQBYP
4
BTL_dcbyp
3:1 Reserved
0
HPFBYP
Type Default
Description
RW 0
1= Bypass MonoOut band-pass filer
RW 1
1= Bypass BTL EQ filter prescale
RW 1
1= Bypass BTL EQ filter
RW 0
1 = bypass BTL DC filter
RO 0
RESERVED
RW 0
1= Bypass BTL high-pass filter (not DC removal filter)
2.29.2.10. PWM4 Register
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset
Register Address
0x13
PWM4
verb F83/783
Bit
Label
Type Default
Description
7
sc_status_clear_right RWC 0
Write once operation will clear sc_fault_status_right
6
sc_status_clear_left RWC 0
Write once operation will clear sc_fault_status_left
5
Reserved
RO 0
RESERVED
4
sc_Fault_status_right RO 0
1 = Fault occurs on right channel
3
sc_Fault_status_left RO 0
1 = Fault occurs on left channel
2:1 scdly_set
RW 00
Used for short circuit detection; designer will set the value
0
evenbit
RW 0
1=Noise Shaper output data are even
IDT™ CONFIDENTIAL
57
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD92