English
Language : 

92HD92 Datasheet, PDF (56/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM
92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset.
Register Address
0x09
verb F79/779
Bit
Label
7
RSVD
6
RSVD
5
RSVD
4
HPPWD
3
SPKRON
2
DMICPWD
1
MCLKOut
0
AUXEn
Type Default
Description
RO 0
Reserved
RO 0
Reserved
RO 0
Reserved
RW 0
Headphone ports are forced off in Aux Audio Mode (including
charge pump)
RW 0
BTL (port D) is forced on in Aux Audio Mode
RW 0
DMIC powered down in Aux Audio Mode (including DAC)
RW 1
MCLK Output Enabler
0 = MCLK Output is disabled in master mode
1 = MCLK is an output in master mode (input in slave mode))
RW 1*
1 = Aux Audio Mode Enabled (on parts supporting Aux Audio
Mode and will override HD Audio power state control to enable
needed paths.)
0 = Aux Audio Mode disabled (power state controlled by HD
Audio rules/controls only.)
Note: The audio interface control is intended to be the same as implemented in non Aux Audio mode but is controlled
through the I2C interface rather than the HD Audio Bus.
2.29.2.6. RESET Register
Register Address
0x0F
RESET
verb F7F/77F
Bit
Label
7:0 RESET
Type Default
Description
RW 0
Writing causes registers to revert to their default values (similar
to a function group reset)
2.29.2.7. STATUS Register
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset
Register Address
0x10
STATUS
verb F80/780
Bit
Label
7
limit1latch
6
limit0latch
5:3 Reserved
2
limit1
1
limit0
0
zerodet_flag
Type Default
Description
RO 0
Latched version of limit1, clear via GAINCTRL_LO[7]
RO 0
Latched version of limit0, clear via GAINCTRL_LO[7]
RO 0x0
RESERVED
RO 0
Set (1) if regz saturation after gain multiply for CH1. may
change on a sample by sample basis.
RO 0
Set (1) if regz saturation after gain multiply for CH0. may
change on a sample by sample basis.
RO 0
Set when input zero detect of long string of zeroes.
IDT™ CONFIDENTIAL
56
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 1.1 1/12
92HD92