92HD92 Datasheet, PDF (53/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
This register reset by POR/DAFG/ULR. Writing to NID22h verb 77F will also cause reset.
Register Address
Bit
Label
7
SCLKINV
0x06
verb F76/776
6
MS
5
LRSWAP
4
LRP
3:2 WL[1:0]
1:0 FORMAT[1:0]
Type Default
Description
RW 0
0 =SCLK not inverted (data and LRCLK transition on falling
edge of SCLK)
1 = invert SCLK (data and LRCLK transition on rising edge of
SCLK)
RW 1
Master/Slave
0 = SCLK and LRCLK are inputs (slave mode)
1 = SCLK and LRCLK are outputs (master mode)
RW 0
Swap Left and Right Samples
0 = Left sample first in frame
1 = Right sample first in frame
RW 0
Left/Right (I2S_LRCLK) Polarity
0 = default per format
1 = LRCLK inverted
RW 10
Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = Reserved
RW 10
link format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = reserved
Note: The audio interface control is intended to be the same as implemented in non Aux Audio mode but is controlled
through the I2C interface rather than the HD Audio Bus.
2.29.2.3. AIC2 Register
Audio Interface (I2S) control in Aux Audio Mode
IDT™ CONFIDENTIAL
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92HD92