92HD92 Datasheet, PDF (47/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
2.28.13. I2C control interface
The CODEC supports I2S I/O also supports a 2-wire (I2C and SMBUS compatible)8-bit slave inter-
face for control while in Aux Audio Mode. The interface supports up to 400KHz operation.
The following must be controlled while in Aux Audio Mode:
6. EQ programming
7. BTL amplifier high-pass filter programming
8. Mono Out path band-pass filter programming
9. BTL amplifier gain
10. Port A mic boost and ADC record gain
11. Dmic0 boost and ADC record gain
2.28.14. Register Write Cycle
The controller indicates the start of data transfer with a high to low transition on SDA while SCL
remains high, signalling that a device address and data will follow. All devices on the 2-wire bus
respond to the start condition and shift in the next eight bits on SDA (7-bit address + Read/Write bit,
MSB first). If the device address received matches the address of the codec and the R/W bit is ‘0’,
indicating a write, then the codec responds by pulling SDA low on the next clock pulse (ACK); other-
wise, the codec returns to the idle condition to wait for a new start condition and valid address.
Once the CODEC has acknowledged a correct address, the controller sends the register address.
the codec acknowledges the register address by pulling SDA low for one clock pulse. The controller
then sends the 8 bits of register data and the codec acknowledges again by pulling SDA low.
When there is a low to high transition on SDA while SCL is high, the transfer is complete. After
receiving a complete address and data sequence the CODEC returns to the idle state. If a start or
stop condition is detected out of sequence, the device returns to the idle condition.
Figure 17. 2-Wire Serial Control Interface
SCL
SDA
START
Device Address DA[6:0]
R/
nW
ACK
Register Address RA[7:0]
ACK
Register Data RD[7:0]
ACK
STOP
2.28.15. Multiple Write Cycle
The controller may write more than one register within a single write cycle. To write additional regis-
ters, the controller will not generate a stop or start (repeated start) command after receiving the
acknowledge for the data payload. Instead the controller will repeat sending 8-bit data payloads. The
register address will increment automatically after receiving each 8-bit payload.
IDT™ CONFIDENTIAL
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92HD92