92HD92 Datasheet, PDF (37/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
SCLK[3:0]
1100
1101
1110
1111
Frequency
(MHz)
7.056
3.528
1.764
PLL clock
divisor
16
32
64
suggested
sample
rate¹
88.2KHz
44.1KHz
44.1KHz
clocks/fr
ame
80
80
40
Notes
reserved
Table 18. SCLK Frequency Selection
1.In ‘Auto’ mode SCLK is referenced to the sample rate (SR[2:0] register bits) but in all other settigns the SCLK rate
is independent of the selected sample rate. Programming a sample rate that uses a different base rate from the
suggested sample rate may cause corruption of the audio stream.
It is possible to invert all clocks (shift, master, and LR clocks) as well as the Port F data input and
Port E data output.
The 92HD93 inverts the clocks and data by default.
Ports are enabled/disabled using the input / output enables defined in the pin widgets.
Aux Audio Mode will be supported and the CODEC will use the MCLK pin as an input in this mode. A
12MHz input will be accepted. (See the Aux Audio section for more information.)
In normal operation, the MCLK pin is an output by default but may be configured as an intput. 8 clock
frequencies are available: 22.5792MHz (512x 44.1K), 11.2896MHz (256x 44.1KHz), 5.6448MHz
(128x 44.1KHz), 28.224MHz (640x 44.1KHz), 14.112MHz (320x 44.1KHz), 7.056MHz (160x
44.1KHz), 24MHz (500x 48KHz), and 12MHz (250x 48KHz - default)
MCLK[2:0]
000
001
010
011
100
101
110
111
Frequency
(MHz)
24
12
22.5792
11.2896
5.6448
28.224
14.112
7.056
PLL clock
divisor
NA
NA
5
10
20
4
8
16
suggested
sample rate
96KHz
48KHz
88.2KHz
44.1KHz
44.1KHz
88.2/96KHz
88.2/48KHz
44.1KHz
Notes
HD Audio BitClk
HD Audio BitClk/2
Table 19. MCLK Frequency Selection
A “bit exact mode” is provided. In this mode, the output path will not alter the data from the DAC con-
verter widget (HD Audio stream data) sent to the I2S output port (Port E.) This means that there is no
sample rate conversion, rounding, filtering or other processing that will change the sample value.
Word length and sample rate are determined by the converter widget connected to the output port
and not by the I2S rate and word length configuration bits. The input port (if used) will have its rate
and word length converted to the requested rate of the ADC converter widget attached to the input
port. The input path may be bit exact if the DAC and ADC converter widgets are programmed to the
same rates and word lengths.
IDT CONFIDENTIAL
37
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD92