92HD92 Datasheet, PDF (48/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Figure 18. Multiple Write Cycle
SCL
SDA
START
Device Address DA[6:0]
R/
nW
ACK
Register Address RA[7:0]
ACK
Register Data RD[7:0]
Register Write 1
ACK
Register Data RD[7:0]
@RA[7:0]+1
ACK
Register Write 2 ...
Register Data RD[7:0]
@RA[7:0]+n
Register Write n
ACK
STOP
2.29. Register Read Cycle
The controller indicates the start of data transfer with a high to low transition on SDA while SCL
remains high, signalling that a device address and data will follow. If the device address received
matches the address of the codec and the R/W bit is ‘0’, indicating a write, then the codec responds
by pulling SDA low on the next clock pulse (ACK); otherwise, the codec returns to the idle condition
to wait for a new start condition and valid address.
Once the codec has acknowledged a correct address, the controller sends a restart command (high
to low transition on SDA while SCL remains high). The controller then re-sends the devices address
with the R/W bit set to ‘1’ to indicate a read cycle.The codec acknowledges by pulling SDA low for
one clock pulse. The controller then receives a byte of register data and the controller acknowledges
by pulling SDA low.
When there is a not acknowledge from the controller and a low to high transition on SDA while SCL
is high, the transfer is complete. If a start or stop condition is detected out of sequence, the device
returns to the idle condition.
Figure 19. Read Cycle
SCL
SDA
START
Device Address DA[6:0]
R/
nW
ACK
Register Address RA[7:0]
Device Address DA[6:0]
ACK
RESTART
R
ACK
Register Data RD[7:0]
nACK
STOP
2.29.1. Multiple Read Cycle
The controller may read more than one register within a single read cycle. To read additional regis-
ters, the controller will not generate a stop or start (repeated start) command after sending the
acknowledge for the second byte of data. Instead the controller will continue to provide clocks and
acknowledge after each byte of transmitted data. The codec will automatically increment the internal
register address after each register has had its data successfully read (ACK from host) but will not
increment the register address if the data is not received correctly by the host (nACK from host) or if
the bus cycle is terminated unexpectedly (however the EQ/Filter address will be incremented even if
the register address is not incremented when performing EQ/Filter RAM reads).
IDT™ CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD92