92HD92 Datasheet, PDF (36/306 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD92
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
2.26. Digital Audio Port (I2S)
Digital Input and Output capability is provided on Port F and Port E..
2.26.1. Characteristics
I2S output is represented as an output port with a headphone output amplifier. I2S input is repre-
sented as an input port. To ensure compatibility with the Microsoft class driver, the port is described
as an analog port and provides the same connectivity as a traditional analog port.
The I2S ports share common clocks. Therefore only one set of configuration controls are required. 2
stereo analog ports are replaced by the Data Input(I2S_DIN), Data output(I2S_DOUT), data
clock(I2S_SCLK), and frame clock (I2S_LRCLK) signals.
Due to the requirement that input and output converters provide independent sample rates, sample
rate conversion support is provided.
Multiple data formats are supported: Left justified, I2S native (Left justified with 1 clock delay), and
Right justified modes. Data lengths of 16, 20 and 24 bits are supported. When there is a mismatch
between the I2S configuration and the HD Audio link programming (converter widget word length)
the word lengths will be aligned using zero padding or truncation as appropriate.
The CODEC may be the clock master or a slave to an external master for the shift clock (SCLK) and
frame clock (LRCLK) signals.
Data shift clock is programmable with a default providing 64 Fs for 44.1KHz based rates and 84Fs
for 48KHz based rates. A 64Fs shift clock is also available for 48KHz rates but the jitter performance
will be much worse than 84Fs. By default, the shift clock will automatically adjust for sample rate.
However, the shift clock may also be programmed to provide a constant output independent of the
selected sample rate.
SCLK[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Frequency
(MHz)
Auto
12.288
6.144
3.072
11.2896
5.6448
2.8224
Auto
16.128
8.064
4.032
PLL clock
divisor
Auto
147/16
147/8
147/4
10
20
40
Auto
7
14
28
suggested
sample
rate¹
All
192KHz
96KHz
48KHz
88.2KHz
88.2KHz
44.1KHz
All
192KHz
96KHz
48KHz
clocks/fr
ame
Notes
64
64
64
64
128
64
64
64/84
84
84
84
SCLK is always 64Fs (48KHz based rates have jitter)
High jitter (<5nS)
High jitter (<5nS)
High jitter (<5nS)
reserved
SCLK adjusts for sample rate. 44.1KHz based rates
are 64Fs and 48KHz based rates are 84Fs
Table 18. SCLK Frequency Selection
IDT CONFIDENTIAL
36
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 1.1 1/12
92HD92