IC-MU_17 Datasheet, PDF (64/66 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.28MM

iC-MU MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.28MM
Rev D1, Page 64/66
REVISION HISTORY
Rel. Rel. Date^∗ Chapter
B1 2013-04-30
Modification
Initial Release
Page
Rel. Rel. Date^∗ Chapter
C1 2015-10-23
Modification
Release for internal use
Page
Rel. Rel. Date^∗ Chapter
Modification
Page
C2 2015-11-02 PACKAGING INFORMATION
Drawing package dimension updated
6
ELECTRICAL
CHARACTERISTICS
Operating conditions: changed VPA, VPD = 5 V in VPA = VPD = 5 V
Item 101: power supply voltage at VPA and VPA combined in item 101
Item 103: changed value min. 3 mA → 8 mA, typ. 8 mA → 13 mA, max. 12 mA → 16 mA
Item 104: changed value min. 25 mA → 20 mA
Item 108: introduced ∆V/∆t Power-Up Slew Rate at VPA and VPD
Item 109: introduced Required Backup Capacitors at VPA, VPD
Item 203: added note: for incremental part see table 78
Item 401: changed value typ. 1.25 V → 1.24 V and max. 1.34 V → 1.36V
Item 404: changed value min. 3.7 V → 3.65V and typ. 4.0 V → 3.9 V
Item 406: changed value min. 0.35 V → 0.3 V
Item 408: introduced max. time for internal cyclic checks
Item 504: changed value +-65 mV to +-60 mV
Item 505: typ. value corrected, typ. 6° → 7°
Item 506: values corrected, min/max 12° → 11.25°, typ. 12.5° → 13°
Item 808 during start-up: changed value 60 kHz → 70 kHz
Item 905: changed value min. 750µA → 800µA and max. -75µA → -80µA
8 to 9
REGISTER ASSIGNMENTS
Renamed REVISION → DEV_ID
16
(EEPROM)
Renamed MANUFACTURER → MFG_ID
SIGNAL CONDITIONING FOR
MASTER AND NONIUS
CHANNELS: x = M,N
Introduced parameter ACGAIN_M, ACGAIN_N, AFGAIN_N, AFGAIN_N
21, 50
I2C INTERFACE AND STARTUP
BEHAVIOR
Table 26: exchanged addr. 0x22 <→ 0x21
Added table 30: default interface depending on PA0
Table 31 corrected
24, 25
CONFIGURABLE I/O INTERFACE
Added note for port A: if MODEA is 0x4, MT sensor communication not possible
(GET_MT = 0)
Added note for port B: if MODEB is 0x0...0x3, pin NER (PB3) is open-collector output
Added Figure 19 and description: parallel SPI bus configuration
27, 33
CONVERTER AND NONIUS
CALCULATION
Parameter FILT table 51: added interpolation factor
Parameter LIN table 53: description enhanced
38, 39
MT INTERFACE
Figure 41 updated
GET_MT description enhanced, added grey note box
MT Interface Daisy Chain description enhanced
43,
27, 44,
63
INCREMENTAL OUTPUT ABZ,
Table 78 SS_AB enhanced
STEP/DIRECTION AND CW/CCW Table 80 CHYS_AB enhanced
46 - 47
REGISTER ACCESS THROUGH
SERIAL INTERFACE (SPI AND
BISS)
Added addr. 0x80 to 0x82. CRC16 and CRC8
Parameter HARD_REV table 92: added code 0x7 → iC-MU Y2
Added Figure 48 register/memory mapping
52, 54
COMMAND REGISTER
iC-MU commands table 102: added code 0x00
Table 103, 104, 105, 106 ’Addr. SER’ corrected
Table 107 corrected
57, 58
DESIGN REVIEW: Notes On Chip iC-MU Y1 - added item no 2: SSI interface (MODEA = 0x4 to 0x7)
63
Functions
Added Notes on chip functions regarding iC-MU chip release Y2 (table 116)