IC-MU_17 Datasheet, PDF (63/66 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.28MM

iC-MU MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.28MM
DESIGN REVIEW: Notes On Chip Functions
Rev D1, Page 63/66
iC-MU Z
No.
Function, Parameter/Code
Description and Application Notes
Please refer to datasheet release A3.
Table 115: Notes on chip functions regarding iC-MU chip release Z.
iC-MU Y1
No.
1
2
3
4
Function, Parameter/Code
CRC of output data iC-MU(2):
IC operating mode BiSS or extended
SSI (MODEA = 0x2, 0x7) and 3-track
nonius with 4096 CPR (MPC = 12,
OUT_LSB = 0x0)
SSI interface (MODEA = 0x4 to 0x7)
SSI interface Gray coded
MODEA = 0x4;
GSSI = 0x1;
OUT_ZERO = 0x0
SSI interface Gray coded with error bit
MODEA = 0x5 or 0x6;
GSSI = 0x1;
OUT_ZERO = 0x0
Description and Application Notes
Effects the construction of a multiturn system with two iC-MU (Page 43):
3-track nonius configuration with 2 iC-MU and 4096 periods, sensor data output
using BiSS or extended SSI protocol (SSI with CRC) shows an invalid CRC.
Data output according to the SSI or SPI protocol is not affected.
MT sensor communication not possible (GET_MT = 0)
The level of the SSI output pin (signal SLO) can be "1" or "0" during timeout t_tos
(see Figure 5). Therefore, a SSI timeout may not be detected by a SSI master in
any case.
To obtain a reliable SSI timeout set parameter OUT_ZERO = 0x1 (includes a zero
bit after position data) and send an additional clock pulse.
The SSI position data is not converted correctly into Gray code.
By setting parameter OUT_ZERO = 0x1 (includes a zero bit after position data)
and sending an additional clock pulse and subsequently ignoring the additional
ZERO bit, the singleturn data is converted correctly into Gray code.
Table 116: Notes on chip functions regarding iC-MU chip release Y1
iC-MU Y2/Y2H
No.
Function, Parameter/Code
1
3-track Nonius systems with two iC-MU
MPC ≥ 0x7
2
SPI interface (MODEA = 0x0, 0x1),
Read/Write REGISTER(single) with
access to EEPROM
3
SSI interface Gray coded
MODEA = 0x4;
GSSI = 0x1;
OUT_ZERO = 0x0
4
SSI interface Gray coded with error bit
MODEA = 0x5 or 0x6;
GSSI = 0x1;
OUT_ZERO = 0x0
Description and Application Notes
The period counter consistency error verification NON_CTR of the multiturn iC-MU
(see Figure 41, iC-MU(2)) must be switched off → NCHK_NON = 0x1.
SPI command sequence as in Figure 30. The end of a Read/Write
REGISTER(single) command to an EEPROM address can be detected by
checking the status bit BUSY. Register Status/Data and SPI-STATUS change
from 0x02 (Busy) to 0x00. The status bits VALID/FAIL are without functionality.
A successful I²C communication between iC-MU and the EEPROM can be
checked via STATUS1 flag EPR_ERR = 0.
The level of the SSI output pin (signal SLO) can be "1" or "0" during timeout t_tos
(see Figure 5). Therefore, a SSI timeout may not be detected by a SSI master in
any case.
To obtain a reliable SSI timeout set parameter OUT_ZERO = 0x1 (includes a zero
bit after position data) and send an additional clock pulse.
The SSI position data is not converted correctly into Gray code.
By setting parameter OUT_ZERO = 0x1 (includes a zero bit after position data)
and sending an additional clock pulse and subsequently ignoring the additional
ZERO bit, the singleturn data is converted correctly into Gray code.
Table 117: Notes on chip functions regarding iC-MU chip release Y2 and Y2H