IC-MU_17 Datasheet, PDF (55/66 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.28MM

iC-MU MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.28MM
STATUS REGISTER AND ERROR MONITORING
Rev D1, Page 55/66
Status register
Various Status-information can be read out via status
bytes STATUS0 and STATUS1.
STATUS0(7:0)
Bit Name
4 STUP
3 AN_MAX
2 AN_MIN
1 AM_MAX
0 AM_MIN
Notes
Addr. SER: 0x76; bit 7:0
R
Description of status message
Startup iC-MU
Signal error^*: clipping (nonius track)
Signal error^*: poor level (nonius track)
Signal error^*: clipping (master track)
Signal error^*: poor level (master track)
Error indication logic: 1 = true, 0 = false,
* _{for signal thresholds see elec. char. no. 508}
and 509
Table 96: Status register 0
Note:
A read access to the reserved addresses SER: 0x3D
and 0x3E also clears the accumulated status informa-
tion STATUS0 and STATUS1 if ACC_STAT is set to
1.
Error and warning bit configuration
The output and the polarity of the error and warning bit
within the different serial protocols (MODEA Table 32)
can be found in Table 99. Messages are allocated to the
error and warning bit by parameter CFGEW according
to Table 100.
STATUS1(7:0)
Bit Name
7 CRC_ERR
6 EPR_ERR
5 MT_ERR
4 MT_CTR
3 NON_CTR
2 FRQ_ABZ
1 FRQ_CNV
0 CMD_EXE
Notes
Addr. SER: 0x77; bit 7:0
R
Description of status message
Invalid check sum internal RAM
I2C communication error:
- No EEPROM
- I2C communication error
Multiturn communication error
Multiturn data consistency error:
counted multiturn ↔ external MT data
Period counter consistency error:
counted period ↔ calculated Nonius position
Excessive signal frequency for ABZ-converter
Excessive signal frequency for internal 12 Bit
converter
Command execution in progress
Error indication logic: 1 = true, 0 = false
Table 97: Status register 1
ACC_STAT configures, if the status registers show the
actual or the accumulated status information.
If the accumulated status is configured, the status bits
are maintained until the status register is read out or
the command ABS_RESET or SOFT_RESET are ex-
ecuted. This is valid except for EPR_ERR, STUP and
CMD_EXE. These bits are set in the status register
independent of the ACC_STAT configuration while the
status information is active. The status register can be
accessed independently of the internal operating state.
MODEA(2:0)
Addr. 0x0B; bit 2:0
Function Error
Warning
low active high active low active
SPI
-
-
-
BiSS
x
-
x
SSI
-
-
-
SSI+ERRL x
-
-
SSI+ERRH -
x
-
ExtSSI
x
-
x
high active
-
-
-
-
-
-
Table 99: MODEA: error/warning-bit within serial proto-
cols
CFGEW(7:0)
Addr. 0x0C; bit 7:0
Bit
Visibility for error bit
7
MT_ERR/MT_CTR
6
NON_CTR
5
Ax_MAX und Ax_MIN
4
EPR_ERR
3
CRC_ERR
2
CMD_EXE
Bit
Visibility for warning bit
1
FRQ_CNV/FRQ_ABZ
0
Ax_MAX und Ax_MIN
Notes
x = M, N
Encoding:
0 = message enabled, 1 = message disabled
Table 100: Error and warning bit configuration
ACC_STAT
Addr. 0x0D; bit 7
Code
Description
0
Output of actual status information
1
Output of accumulated status information
Table 98: Output configuration of status register
If an error pin is configured using MODEB (Table 33),
an internal error (see status register, ACC_STAT con-
figuration and error bit configuration with CFGEW) is
signaled by the NER pin (PB3). In that case pin PB3 is
a open-collector output. The minimum message time
for I/O pin NER can be set by EMTD.