IC-MHM Datasheet, PDF (52/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
CONFIGURATION
Rev D1, Page 52/63
Before use, the iC-MHM must be configured for the
intended application. Configuration consists of writ-
ing values for all the configuration parameters (refer to
CONFIGURATION PARAMETERS on page 15) using
the serial interface in BiSS or SPI mode and option-
ally storing the configuration data and checksums in an
attached EEPROM for use on subsequent start ups.
cycle with CDM = 0 and CDM = 1, and a four BiSS cycle
extract for a CDM sequence of 0b0010.
MA
SLO
T(MA)
Cycle
timeout
Figure 39: BiSS Cycle with CDM = 0
The configuration is protected by its own checksum.
MA
CRC_CFG
Name
0x00
...
0xFF
Addr. Address 0x0C;
Description
Checksum for address range 0x00 to 0x0B;
CRC polynomial 0x11D
x⁸ + x⁴ + x³ + x² + 1 (CRC-8)
start value 0x02
SLO
T(MA)
Cycle
timeout
Figure 40: BiSS Cycle with CDM = 1
MA
SLO
0
0
1
0
Table 97: Configuration Data Checksum
Figure 41: BiSS Cycle Extract for CDM Sequence
0b0010
Initial Configuration
The first time the iC-MHM is powered up, either with
an un-programmed EEPROM or no EEPROM, configu-
ration fails. This activates the error output (pin NERR
low), and drives SLO high to indicate the error. At this
point, the configuration parameters are all zero and the
iC-MHM must be configured via the serial interface in
BiSS or SPI mode. At least a minimum configuration
must be done and the chip reset to clear the error out-
put and release SLO to restore full BiSS bidirectional
communication.
After a configuration failure due to an un-programmed
EEPROM, no EEPROM, or a configuration or offset
CRC failure, the iC-MHM serial port is in the following
state:
Serial interface: TTL/RS-422 I/O (RTX_MODE = 0)
Multiturn feedthrough mode disabled (GET_MTI = 0)
BiSS enabled (DISBISS = 0)
SSI disabled (ENSSI = 0)
Register protection disabled (REGPROT = 0)
Command protection disabled (INSPROT = 0)
In BiSS mode, bidirectional communication is not possi-
ble at this point because SLO is driven high and SLI is
ignored. Thus, the initial configuration must be written
"blind" as no data is sent back from the iC-MHM. For
initial configuration using BiSS mode communication,
the iC-MHM is always slave 0.
Since each BiSS cycle transmits only a single CDM
bit, it can be reduced to four clock cycles plus the time-
out. The following Figures show such a single BiSS
To enable full bidirectional BiSS communication after
a configuration failure due to an un-programmed EEP-
ROM, no EEPROM, or a configuration or offset CRC
failure, the BiSS interface must be initialized with val-
ues for parameters RTX_MODE, GET_MTI, DISBISS,
ENSSI, REGPROT, and INSPROT. This means that at
a minimum, registers 0x02, 0x03, 0x07, and 0x0B must
be initialized.
A single BiSS register write requires 14 BiSS cycles
with CDM = 0 followed by 32 cycles of BiSS C register
communication data. Following is an example BiSS se-
quence to reset registers 0x02, 0x03, 0x07, and 0x0B
and then reset the iC-MHM (0x74 = 0x01).
"00000000000000"
"1 1 000 0000010 0000 0 1 1 00000000 1111 0"
"00000000000000"
"1 1 000 0000011 0011 0 1 1 00000000 1111 0"
"00000000000000"
"1 1 000 0000111 1111 0 1 1 00000000 1111 0"
"00000000000000"
"1 1 000 0001011 1000 0 1 1 00000000 1111 0"
"00000000000000"
"1 1 000 1110100 0010 0 1 1 00000001 1100 0"
Refer to the BiSS Interface Protocol Description (C-
Mode) at www.biss-interface.com for more information
on BiSS register communication.
BiSS Mode Configuration
After writing the communication configuration and re-